1. Field of the Invention
This invention relates to a differential detector circuit, comprised of a plurality of MOSFETs fabricated, in a preferred embodiment, by silicon on sapphire techniques for reading binary data from an array of memory cells.
2. Prior Art
A conventional array of memory cells includes pairs of data bus lines, by which to write and read information signals, and a row or address select line, by which to select from the array a particular memory cell to be accessed. Typically, a sense circuit associated with the array of memory cells is comprised of a detector circuit and a memory output driver which are connected to each of the pairs of data bus lines. Information is read from each of the memory cells forming the array by utilizing differential sensing of signals along the data bus lines.
Conventional detector circuits are relatively insensitive to the signals supplied along the data bus lines. In order to tolerate the low sensitivity of the detector circuit, it has heretofore been a common technique to undesirably limit the number of memory cells in the array. Another conventional technique is to increase the storage capacitance of each memory cell, thereby increasing the ratio of the storage capacitance to the capacitance along the bus lines. However, as a result thereof, the larger storage capacitance must first be charged when addressing a memory cell in order to read out data. Thus, the read operation is undesirably slowed.
When the detector circuit is comprised of field effect transistors fabricated from a layer of silicon on a sapphire substrate (SOS), it is customary, in the prior art, to allow the substrate under each one of the SOS transistors to float free from any source of potential. Consequently, the body node (i.e. a lightly doped region formed under the channel region of the SOS transistor) also floats free from any source of potential. This has a further effect of minimizing the sensitivity of the detector and the size of an output signal therefrom.